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PCK351
1:10 clock distribution device with 3-State outputs
Rev. 01 -- 14 May 2002 Product data
1. Description
The PCK351 is a high-performance 3.3 V LVTTL clock distribution device. The PCK351 enables a single clock input to be distributed to ten outputs with minimum output skew and pulse skew. The use of distributed VCC and GND pins in the PCK351 ensures reduced switching noise. The PCK351 is characterized for operation over the supply range 3.0 V to 3.6 V, and over the industrial temperature range -40 to +85 C.
2. Features
s s s s s s s s s s 1:10 LVTTL clock distribution Low output to output skew Low output pulse skew Over voltage tolerant inputs and outputs LVTTL-compatible inputs and outputs Distributed VCC and ground pins reduce switching noise Balanced High-drive outputs (-32 mA IOH, 32 mA IOL) Reduced power dissipation due to the state-of-the-art QUBiC-LP process Supply range of +3.0 V to +3.6 V Package options include plastic small-outline (D) and shrink small-outline (DB) packages s Industrial temperature range -40 to +85 C s PCK351 is identical to and replaces PTN3151.
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf 3.0 ns. Symbol tPHL/tPLH CI CO CPD
[1]
Parameter propagation delay: A to Yn input capacitance output capacitance power dissipation capacitance[1]
Conditions CL = 50 pF; VCC = 3.3 V VI = VCC or GND VI = VCC or GND CL = 50 pF; f = 1 MHz
Min 3.1 -
Typ 3.6 4 6 48
Max 4.1 -
Unit ns pF pF pF
CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts.
4. Ordering information
Table 2: Ordering information Package Name PCK351D PCK351DB SO24 SSOP24 Description plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm Version SOT137-1 SOT340-1 Type number
9397 750 09791
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
2 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
5. Pinning information
5.1 Pinning
GND Y10 VCC Y9 OE A GND GND Y8
1 2 3 4 5
24 GND 23 Y1 22 VCC 21 Y2 20 GND
GND 1 Y10 2 VCC 3 Y9 4 OE 5
24 GND 23 Y1 22 VCC 21 Y2 20 GND
6 7 8 9
19 Y3 18 Y4 17 GND 16 Y5 15 VCC 14 Y6 13 GND
PCK351DB
PCK351D
A6 GND 7 GND 8 Y8 9 VCC 10 Y7 11 GND 12
19 Y3 18 Y4 17 GND 16 Y5 15 VCC 14 Y6 13 GND
VCC 10 Y7 11 GND 12
002aaa280
002aaa281
Fig 1. SO24 pin configuration.
Fig 2. SSOP24 pin configuration.
5.2 Pin description
Table 3: Symbol GND Y10 to Y1 VCC OE A Pin description Pin 1, 7, 8, 12, 13, 17, 20, 24 2, 4, 9, 11, 14, 16, 18, 19, 21, 23 3, 10, 15, 22 5 6 Description ground (0 V) outputs supply voltage output enable input (Active-LOW) data input
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Product data
Rev. 01 -- 14 May 2002
3 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
6. Functional description
6.1 Function table
Table 4: Function table Inputs A L H L H
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
Outputs OE H H L L Yn Z Z L H
6.2 Logic symbol
OE
5
EN
23 21 19 18 A 6 16 14 11 9
Y1 Y2 Y3 Y4 Y5 Y6
Y7 Y8 4 Y9 2 Y10
002aaa283
Fig 3. Logic symbol.
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(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
4 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
6.3 Logic diagram
5
OE
23
Y1
21
Y2
19
Y3
18 A 6 16
Y4
Y5
14
Y6
11
Y7
9
Y8
4
Y9
2
Y10
002aaa282
Fig 4. Logic diagram.
9397 750 09791
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
5 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
7. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1], [2] Symbol VCC VI VO IIK IOK IO ICC, IGND Tstg PD Parameter supply voltage range input voltage range output voltage range input clamp current output clamp current output sink current VCC or GND current storage temperature maximum power dissipation SO package SSOP package
[1]
[3] [3]
Conditions
Min -0.5 -0.5 -0.5 -65
Max +4.6 +7.0 +3.6 -18 -50 64 75 +150 0.65 1.7
Unit V V V mA mA mA mA C W W
VI < 0 V VI < 0 V
Tamb = +55 C Tamb = +55 C
-
[2]
[3]
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under `recommended operating conditions' is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. The input and output negative voltage ratings may be exceeded if the input and output clamp currents are observed.
8. Recommended operating conditions
Table 6: Recommended operating conditions See note 1. Symbol VCC VIH VI Tamb Parameter supply voltage HIGH-level input voltage input voltage ambient temperature see Table 7 "DC characteristics" and Table 8 "AC characteristics" per device VCC = 3.3 0.3 V Conditions Min 3.0 2.0 0 -40 Max 3.6 5.5 0.8 +85 Unit V V V C
tr, tf
[1]
input rise and fall times
-
100
ns/V
Unused pins (input or I/O) must be held HIGH or LOW.
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(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
6 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
9. Static characteristics
Table 7: DC characteristics Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = 25 C. Symbol VIK VOH VOL ILI ILO IOZ ICC Parameter input diode voltage HIGH-level output voltage LOW-level output voltage input leakage current output leakage current 3-State output OFF-state current quiescent supply current Conditions VCC = 3.0 V; II = -18 mA VCC = 3.0 V; IOH = -32 mA VCC = 3.0 V; IOL = 32 mA VCC = 3.6 V; VI = GND or 5.5 V VCC = 3.6 V; VO = 2.5 V VCC = 3.6 V; VO = 3 V VCC = 3.6 V; VI = VCC or GND; IO = 0; outputs HIGH VCC = 3.6 V; VI = VCC or GND; IO = 0; outputs LOW VCC = 3.6 V; VI = VCC or GND; IO = 0; outputs disabled CI CO input capacitance output capacitance VCC = 3.3 V; VI = VCC or GND; f = 10 MHz VCC = 3.3 V; VO = VCC or GND; f = 10 MHz
[1]
Min 2.0 -15 -
Typ 4 6
Max -1.2 0.5 1.0 -150 10 0.3 25 0.3 -
Unit V V V A mA A mA mA mA pF pF
[1]
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
9397 750 09791
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
7 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
10. Dynamic characteristics
Table 8: AC characteristics GND = 0 V; tr = tf 3.0 ns. Symbol tPLH/tPHL tPZH/tPZL tPHZ/tPLZ tsk(o) tsk(p) tsk(pr) tr tf tPLH/tPHL tPZH/tPZL tPHZ/tPLZ tsk(o) tsk(p) tsk(pr) tr tf Parameter propagation delay A to Yn propagation delay OE to Yn propagation delay OE to Yn output-to-output skew A to Yn pulse skew A to Yn part-to-part skew A to Yn rise time A to Yn fall time A to Yn propagation delay A to Yn propagation delay OE to Yn propagation delay OE to Yn output-to-output skew A to Yn pulse skew A to Yn part-to-part skew A to Yn rise time A to Yn fall time A to Yn Conditions CL = 50 pF; see Figures 5 and 8 CL = 50 pF; see Figures 6 and 8 CL = 50 pF; see Figures 6 and 8 CL = 50 pF; see Figures 7 and 8 CL = 50 pF; see Figures 7 and 8 CL = 50 pF; see Figures 7 and 8 CL = 50 pF; see Figures 5 and 8 CL = 50 pF; see Figures 5 and 8 CL = 50 pF; see Figures 5 and 8 CL = 50 pF; see Figures 6 and 8 CL = 50 pF; see Figures 6 and 8 CL = 50 pF; see Figures 7 and 8 CL = 50 pF; see Figures 7 and 8 CL = 50 pF; see Figures 7 and 8 CL = 50 pF; see Figures 5 and 8 CL = 50 pF; see Figures 5 and 8 Min 3.1 1.8 1.8 1.3 1.7 Typ 3.6 3.8 4.0 0.3 0.2 Max 4.1 5.5 5.9 0.5 0.8 1 5.9 6.3 0.5 0.8 1 1.5 1.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VCC = 3.3 V; Tamb = 25 C
VCC = 3.3 to 3.6 V; Tamb = 0 C to +70 C
Table 9: Switching characteristics Temperature and VCC coefficients over recommended operating free-air temperature and VCC range; note 1. Symbol tPLH(T) tPHL(T) tPLH(V) tPHL(V) Parameter temperature coefficient of LOW-to-HIGH propagation delay A to Yn (average value) temperature coefficient of HIGH-to-LOW propagation delay A to Yn (average value) VCC coefficient of LOW-to-HIGH propagation delay A to Yn (average value) VCC coefficient of HIGH-to-LOW propagation delay A to Yn (average value) Conditions note 2 note 2 note 3 note 3 Max 65 45 -140 -120 Unit ps/10 C ps/10 C ps/100 mV ps/100 mV
[1] [2] [3]
These data were extracted from characterization material and are not tested at the factory. tPLH(T) and tPHL(T) are virtually independent of VCC. tPLH(V) and tPHL(V) are virtually independent of temperature.
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Product data
Rev. 01 -- 14 May 2002
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Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
10.1 AC waveforms
3.0 V A input 0V tPHL VOH Yn output VOL tr tf
002aaa289
1.5 V
tPLH
2V 1.5 V 0.8 V
Fig 5. The input (A) to outputs (Yn) propagation delays and rise and fall times.
3V OE input 0V tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs disabled outputs disabled outputs disabled
002aaa290
1.5 V
tPZL
1.5 V VOL + 0.3 V tPZH VOH - 0.3 V 1.5 V
Fig 6. 3-State enable and disable times.
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(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
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Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
A input
Y1 output tPHL1 tPLH1
Y2 output tPHL2 tPLH2
Y3 output tPHL3 tPLH3
Y4 output tPHL4 tPLH4
Y5 output tPHL5 tPLH5
Y6 output tPHL6 tPLH6
Y7 output tPHL7 tPLH7
Y8 output tPHL8 tPLH8
Y9 output tPHL9 tPLH9
Y10 output tPHL10 tPLH10
002aaa286
(1) Output-to-output skew is the highest values of positive and negative edge skew: tsk(o) = tPLHn(max) - tPLHn(min) and tsk(o) = tPHLn(max) - tPHLn(min) for n = 1 to 10. (2) Output pulse skew is the highest value of: tsk(p) = |tPLHn - tPHLn| for n = 1 to 10. (3) Part-to-part skew tsk(pr) represents the positive and negative edge skew between outputs of several devices operating under identical conditions.
Fig 7. Calculation of tsk(o), tsk(p), and tsk(pr).
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Product data
Rev. 01 -- 14 May 2002
10 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
S1 VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF 500 VO 500
6V open GND
002aaa285
TEST
tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 6V
S1
open GND
Fig 8. Load circuitry for switching times.
9397 750 09791
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
11 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
11. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
Fig 9. SO24 package outline (SOT137-1).
9397 750 09791 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
12 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
Fig 10. SSOP24 package outline (SOT340-1).
9397 750 09791 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
13 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
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(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
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Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
12.5 Package related soldering information
Table 10: Package[1] BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[4], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[3] suitable not recommended[4][5] not recommended[6] Reflow[2] suitable suitable suitable suitable suitable
[3]
[4] [5] [6]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
13. Revision history
Table 11: Rev Date 01 20020514 Revision history CPCN Description Product data; initial version. Engineering Change Notice 853-2344 28198.
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(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
15 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
14. Data sheet status
Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] [2]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
15. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
16. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 09791
Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 14 May 2002
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Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 7 8 9 10 10.1 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Logic symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 15 Package related soldering information . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
(c) Koninklijke Philips Electronics N.V. 2002. Printed in the U.S.A
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 May 2002 Document order number: 9397 750 09791

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